The present invention relates to a nonvolatile semiconductor memory device comprising a non volatile memory cell controlled by a control gate.
A MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -substrate) type is known as one example of the nonvolatile semiconductor memory device. In this type, a gate insulating layer between a channel and a gate is constructed by a laminating layer body of a silicon oxide film, a silicon nitride film and a silicon oxide film, and electric charges are trapped in the silicon nitride film.
This MONOS type nonvolatile semiconductor memory device is disclosed in a publication: Y. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers, p.122-p.123. In this publication, a MONOS flash memory cell having two nonvolatile memory cells (also called MONOS memory elements or cells) controlled by one word gate and two control gates is disclosed. Namely, one flash memory cell has two trap sites of the electric charges.
A memory cell array region is constructed by arranging a plurality of MONOS flash memory cells having such a structure in row and column directions.
Two bit lines, one word line and two control gate lines are required to operate this MONOS flash memory cell. In this case, when many memory cells are operated, these lines can be commonly connected when the same potential is set even in a different control gate.
There are erasion, a program and reading of data in the operation of the flash memory of this kind. The program and the reading of data are normally simultaneously executed by a selection cell (selected nonvolatile memory cell) of 8 bits or 16 bits.
Here, in the MONOS flash memory, a plurality of MONOS flash memory cells not separated in elements from each other are connected to one word line. When the read or the program of data is executed with respect to a certain specific selection cell, the voltage of the MONOS flash memory having this selection cell must be set and the voltage of a MONOS flash memory cell adjacent to this MONOS flash memory must be also suitably set.
For example, a case in which one of the memory cells is a selection cell and the other is a non-selection cell (called an opposite cell), will be considered. When data are read from the selection cell, a selection voltage is supplied to the control gate of the selection cell, and an override voltage is supplied to the control gate of the opposite cell, and 0 V is supplied to the control gate of the non-selection cell except for the opposite cell. These voltages are similarly supplied when data is programmed except that the values of the selection voltage and the override voltage at the data program time are merely different from those at the data read time.
Here, the override voltage is a voltage required to flow a read current or a program current by turning-on a transistor of the opposite cell irrespective of the existence or nonexistence of the program of the opposite cell.
Here, the override voltage at the data read time, and the selection voltage and the override voltage at the data program time are higher than a power supply voltage, and are supplied from a booster circuit.
When a memory address is changed at the read or program time, a through current is generated at a switching time in a control gate driver for switching the voltage of the control gate, and the voltage of the voltage raising circuit as a supply source of the control gate voltage drops.
Therefore, the present invention may provide a nonvolatile semiconductor memory device able to reduce a current consumption by preventing the voltage from dropping in the voltage raising circuit which generates the control gate voltage.
A nonvolatile semiconductor memory device according to the present invention comprises:
a memory cell array region in which a plurality of nonvolatile memory cells are arranged, each of the nonvolatile memory cells comprising a control gate; and
a control gate voltage generation section which generates a voltage driving the control gate of each of the nonvolatile memory cells in the memory cell array region,
wherein the control gate voltage generation section includes:
a booster circuit which generates a plurality of voltages; and
a voltage control circuit which comprises a plurality of voltage input terminals and a plurality of voltage output terminals, the voltage control circuit switching and outputting the voltages from the booster circuit through the voltage input terminals to the voltage output terminals in accordance with a selection state of the nonvolatile memory cells, and
wherein the voltage control circuit is set to a disconnection state, in which no voltage is outputted from the voltage raising circuit to any of the voltage output terminals, before the voltages are outputted from the voltage output terminals.
In accordance with the present invention, the voltage control circuit is disconnected from the voltage raising circuit before the voltages for the control gate are outputted from the voltage control circuit. Accordingly, no voltage drop in the voltage raising circuit occurs even when a through current flows within a control gate voltage supply path at a switching time when the control gate voltages are switched and outputted in the voltage control circuit.
The nonvolatile semiconductor memory device of the present invention may further include: a plurality of control gate drivers, each of the control gate drivers including a CMOS transistor which selects one voltage between one of the voltages from the voltage control circuit and a voltage equal to or lower than a ground voltage, and supplies the selected voltage to the control gate. The CMOS transistor may be switched in accordance with a change of a memory address. In this case, the voltage control circuit may be set to the disconnection state in a period including a switching period in the CMOS transistor.
Thus, no voltage in the voltage raising circuit drops even when the through current flows at the switching time in the CMOS transistor.
An address transition signal changing at a transition time of the memory address may be used as timing for setting the voltage control circuit to the disconnection state. The voltage control circuit maybe set to the disconnection state over a predetermined period based on the address transition signal.
The voltage control circuit may output a predetermined voltage from the voltage output terminals during the disconnection state. The predetermined voltage may be set to a power supply voltage. Thus, the switching can be performed by using the power supply voltage and the control gate can be pre-driven by the power supply voltage during a disconnecting period from the voltage raising circuit.
The voltage control circuit may have first and second voltage input terminals, a power input terminal and first and second voltage output terminals. In this case, the voltage control circuit may control switching of a connection state between the first and second voltage input terminals and the first and second voltage output terminals in accordance with the selection state of the nonvolatile memory cells. Further, the voltage control circuit may control a connection between the power input terminal and the first and second voltage output terminals in the disconnection state.
In this case, at a data read time in the voltage control circuit, a first control gate selection voltage may be supplied to the first voltage input terminal, and a first override voltage maybe supplied to the second voltage input terminal by the voltage raising circuit, the first control gate selection voltage being lower than the power supply voltage. On the other hand, at a data program time in the voltage control circuit, a second control gate selection voltage may be supplied to the first voltage input terminal, and a second override voltage may be supplied to the second voltage input terminal by the voltage raising circuit, the second control gate selection voltage being higher than the power supply voltage, and the second override voltage being higher than the first override voltage.
In the present invention, the voltage control circuit may further include a first P-type transistor and a second P-type transistor, and the drains of the first and second P-type transistors may be connected to each other, the first P-type transistor having a source connected to the first voltage input terminal, and the second P-type transistor having a source connected to the power input terminal. In this case, a well voltage varying circuit which varies well voltages of the first and second P-type transistors may be further provided. The well voltage varying circuit may set the well voltage to the power supply voltage at the data read time, and may set the well voltage to the second override voltage at the data program time.
Thus, it is possible to prevent a reverse current from flowing into the well through a PN diode between the drain and the well in each of the first and second P-type transistors at the data read time and the data program time.
The present invention may be applied to a nonvolatile semiconductor memory device in which memory cells are arranged in a row direction and a column direction in the memory cell array region, each of the memory cells having one word gate, and first and second nonvolatile memory cells controlled by first and second control gates. The nonvolatile semiconductor memory device having a memory cell structure except for the memory cell may be also used.
Each of the first and second nonvolatile memory cells constituting the memory cell may have an ONO film formed of an oxide film (O), a nitride film (N) and an oxide film (O) as a trap site of electric charges. In addition, other types of trap structure can be adopted.